发明名称 |
Counter circuit using Johnson-type counter and applied circuit including the same |
摘要 |
A counter circuit includes Johnson-type counters of m stages, each counter including a plurality of flip-flops connected in a cascade connection, each flip-flop receiving a clock signal at a respective clock input end. In the constitution, signals at respective output ends of flip-flops in a (k-1)-th stage counter are simultaneously input to respective clock input ends of flip-flops in each counter of a k-th stage and more. As a result, it is possible to obtain a signal having an arbitrary ratio of frequency division with high speed, while relatively simplifying the circuit constitution.
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申请公布号 |
US5321733(A) |
申请公布日期 |
1994.06.14 |
申请号 |
US19920928469 |
申请日期 |
1992.08.12 |
申请人 |
FUJITSU LIMITED |
发明人 |
TAMAMURA, MASAYA;SHIOTSU, SHINICHI;NOMURA, KATSUNOBU |
分类号 |
H03K23/54;H03M9/00;(IPC1-7):H03K21/02 |
主分类号 |
H03K23/54 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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