发明名称 Dual slice architectures for programmable logic devices
摘要 Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.
申请公布号 US7385417(B1) 申请公布日期 2008.06.10
申请号 US20060446542 申请日期 2006.06.02
申请人 LATTICE SEMICONDUCTOR CORPORATION 发明人 AGRAWAL OM P.;HE XIAOJIE;WIJESURIYA SAJITHA;BRITTON BARRY;DING MING H.;ZHAO JUN
分类号 G06F7/38;H03K19/173 主分类号 G06F7/38
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