| 摘要 |
A semiconductor memory and a system are provided to evaluate a real signal line and a real memory cell adjacent to a dummy signal line sufficiently, by having equal characteristics of signals supplied to the dummy signal line and the real signal line. A semiconductor memory includes a real memory cell and a dummy memory cell. A real signal line is connected to the real memory cell. A dummy signal line is arranged in the outside of the real signal line, and is connected to the dummy memory cell. A real driver drives the real signal line by being synchronized with a timing signal. A dummy driver drives the dummy signal line by being synchronized to the timing signal. An operation control circuit generates the common timing signal supplied to the real driver and the dummy driver.
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