| 摘要 |
809,390. Transistor limiter circuits. PHILIPS ELECTRICAL INDUSTRIES Ltd. Jan. 25, 1957 [Jan. 28, 1956], No. 2767/57. Class 40 (6). A transistor limiter circuit comprises a tuned input circuit connected to a limiter of the type in which the limiter bias is determined by the incoming signal and also connected to the input of a transistor which is arranged to operate as a collector limiter and which, by variation of its input impedance, effects further limitation of the input signal. In Fig. 2 a series tuned input circuit 1, 2 is connected to a limiter circuit comprising rectifier 7 capacitor 5<1> and resistors 15, 6<1>. The D.C. voltage which is thus developed across resistors 15, 16 is used to bias the limiter. Part of the voltage is also used as the collector bias for a grounded base transistor amplifier 3 and part as the emitter bias, the latter serving to maintain the emitter conductive during negative half cycles of the input wave so as to complete the series tuned input circuit. The collector bottoms during peaks of the input signals so as to further limit the signal amplitude and this reflects an increased impedance at the emitter which damps the series tuned input circuit causing still further limitation. The bias for the emitter may be omitted in which case a rectifier must be connected between emitter and base to complete the input tuned circuit during negative half-cycles (Fig. 1, not shown). In Fig. 3 (not shown) a parallel tuned input circuit is used and the common base amplifier is replaced by one of common emitter type. |
