Phase locked loop, phase locked loop method and semiconductor device having phase locked loop

摘要

A phase locked loop (PLL) circuit may include a phase difference detecting and control signal generating portion, a voltage control oscillator, and/or an initial control voltage generating portion. The phase difference detecting and control signal generating portion may be configured to detect a phase difference between an input clock signal and an output clock signal to control a voltage level of a control signal. The voltage control oscillator may be configured to vary a frequency of the output clock signal in response to the voltage level of the control signal. The initial control voltage generating portion may be configured to receive the input clock signal, calculate a locking control voltage corresponding to the input clock signal, and/or cause the voltage level of the control signal to become a level of the locking control voltage from power up of the phase locked loop circuit.