| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of further improving a breakdown withstand voltage against an inside ESD. SOLUTION: An output circuit 14 has a plurality of transistor pairs 33 comprising a pMOS transistor 31 and an nMOS transistor 32 each, and the plurality of transistor pairs 33 are grouped into a first transistor group 34 comprising at least one transistor pair 33 connected between a signal electrode 15 and a signal line 16 to constitute a CMOS inverter, and a second transistor group 35 comprising the other transistor pair 33 not constituting the CMOS inverter. Each tansistor pair 33 of the second transistor group 35 has a source, a gate, and a drain of the pMOS transistor 31 connected to the plus side power line 27, and a source, a gate, and a drain of the nMOS transistor 32 connected to the minus side power line 29. COPYRIGHT: (C)2008,JPO&INPIT |
