发明名称 FAST ARIA BLOCK ENCRYPTION/DECRYPTION APPARATUS
摘要 A fast aria block encryption and decryption apparatus is provided to reduce the number of clock cycles used in encryption remarkably by increasing the number of rounds which can be calculated in a first clock and to downsize a hardware without an additional key initializing circuit by performing a key initializing process with a round operation unit. The fast aria block encryption and decryption apparatus performs encryption and decryption operation and key initialization process through following parts: the first round operation part to significantly reduce the number of clock cycle required in case of encryption, perform exclusive OR operation for input data of an object for encryption and decryption or an operation result of even number round and a key of odd number round, perform substitution operation to the result of exclusive OR operation, and perform diffusion operation for the result of exclusive OR operation(15); the second round operation part to perform exclusive OR operation for the result of the first round operation part and even number round key, substitution operation for the result of exclusive OR operation, and diffusion operation for the result of substitution operation(17); the first XOR period to perform exclusive OR operation for the result of substitution operation process of the second round operation part on the final round and the key for the final round, and print data for aria block encryption and decryption(18); and a part to perform encryption and decryption operation and key initialization process through round key generation part which generates and provides round key value needed to the operation of the first and second round operation part from the initial key value acquired from master key(25).
申请公布号 KR100786391(B1) 申请公布日期 2007.12.17
申请号 KR20060095008 申请日期 2006.09.28
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 LEE, SANG WOO;JEON, YONG SUNG;KIM, KI YOUNG;JANG, JONG SOO
分类号 G06F7/00;G06F1/00 主分类号 G06F7/00
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