发明名称 |
Data Generator Having Stable Duration From Trigger Arrival to Data Output Start |
摘要 |
A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing the address after the trigger signal. A hexadecimal counter counts a clock that is faster than the divided clock as the counted number circulates every one period of the divided clock . A trigger information latch latches the counted number of the counter when the trigger signal arrives and provides it to a MUX. The MUX selects data in a pair of the parallel data provided at first and second inputs I<SUB>1 </SUB>and I<SUB>2 </SUB>to produce rearranged parallel data bits according to the latched counted number. A parallel to serial converter receives the rearranged parallel data to convert it to serial data according to the clock.
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申请公布号 |
US2007247927(A1) |
申请公布日期 |
2007.10.25 |
申请号 |
US20070738485 |
申请日期 |
2007.04.21 |
申请人 |
TEKTRONIX INTERNATIONAL SALES GMBH |
发明人 |
MIKI YASUHIKO |
分类号 |
G11C7/10 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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