Semiconductor memory device testing device, has address supply circuit supplying memory input bits with memory input addresses to semiconductor memory device, where memory input bits are inputted by logical operation circuits

摘要

The testing device (10) has logical operation circuits outputting image data for memory input bits by executing a predetermined logical operation with a masking effect by using an arithmetic masking circuit. An address supply circuit supplies memory input bits with memory input addresses to a semiconductor memory device (100), where the memory input bits are inputted by the logical operation circuits. A translation memory receives a translation address, which consists of bits of a part of a physical address and outputs data as a determination address. Independent claims are also included for the following: (1) a program provided for a control device for controlling a testing device (2) a method for testing a memory by a testing device.