| 摘要 |
A processor according to the present invention includes a decoding unit 20 , an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC 0 ~VC 3 ( 110 ) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C 4 and C 5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC 0 ~VC 3 are zero, and (ii) sets the condition flags C 4 and C 5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC 0 ~VC 3 are stored in the condition flags C 0 ~C 3.
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