发明名称 System and method for test generation for system level verification using parallel algorithms
摘要 A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.
申请公布号 US7260495(B2) 申请公布日期 2007.08.21
申请号 US20050146987 申请日期 2005.06.06
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 GUPTA SANJAY;ROBERTS STEVEN L.;SPANDIKOW CHRISTOPHER J.
分类号 G06F11/00 主分类号 G06F11/00
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