| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the number of test patterns without increasing the area of a semiconductor integrated circuit, and without lowering a failure detection rate, in an actual-speed scan test of the semiconductor integrated circuit operated in a plurality of clocks. <P>SOLUTION: A test board 100 is equipped with semiconductor integrated circuits 120-122 equipped with a plurality of scan chain groups drivable in a clock having a different frequency, clock control circuits 110-112 and a controller 101 for assigning successively all combinations of the plurality of clocks having mutually different frequencies to each semiconductor integrated circuit, and a selector group 102 for selecting each output from the scan chain groups driven in the assigned clock and supplying it to an inspection device. <P>COPYRIGHT: (C)2007,JPO&INPIT |
