| 摘要 |
A semiconductor integrated circuit apparatus and an electronic apparatus are provided to lower largely an on-resistance by preventing a leakage current in a cutoff state of a power control MOS transistor. A logic circuit(110) includes a plurality of Nch MIS transistors and a plurality of Pch MIS transistors(PT11,PT12). A first pseudo power supply line(VDD1) is connected to a high potential power supply terminal of the logic circuit. A second pseudo power supply line(VSS1) is connected to a low potential power supply terminal of the logic circuit. A first Nch MIS transistor has a threshold voltage smaller than an absolute value of a threshold voltage of the MIS transistors of the logic circuit, or the first Nch MIS transistor is a depletion type. The second pseudo power supply line is connected to a drain of the first Nch MIS transistor. A low potential power supply line is connected to a source of the first Nch MIS transistor. A voltage having a low level lower than a potential of the low potential power supply line and a high level higher than the potential of the low potential power supply line is applied to a gate of the first Nch MIS transistor.
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