| 摘要 |
A Zero IF receiver (1) has a demodulator (15) that can either demodulate both an I signal component output by an I channel (12) and a Q signal component output by a Q channel (13) to output a dual channel demodulated signal or demodulate just the I signal component output by the I channel (12) to output a single channel demodulated signal. A controller (16) causes output of the dual channel demodulated signal or the single channel demodulated signal by selectively disabling the Q channel. When the dual channel demodulated signal is output by the demodulator (15), the values of bits in the signal can be determined in a conventional way. When the single channel signal is output by the demodulator (15), only transitions between bits of different value can be identified. However, these transitions can be used by a decoder (17) in combination with a value of a bit previously determined from the dual channel demodulated signal to continue to output bit values. So, the signal can be demodulated and decoded even when the controller (16) disables the Q channel (13) for much of the time. |
