| 摘要 |
A transistor and a fabricating method the same are provided to reduce remarkably capacitance between a gate and a drain by forming an ultra-low-dielectric on a gate oxide layer corresponding to a bottom surface of a trench. A transistor includes a drain electrode(10), a substrate(20) positioned on the drain electrode, a drain region(30) formed on the substrate, a main body(40) formed on the drain region, a plurality of source regions(50) formed partially on the main body, a trench(60) formed on the source regions, the main body, and the drain region, a gate oxide layer(70) formed in the trench, a doped polysilicon(80) formed on the gate oxide layer of the trench, an insulating layer(90) formed on the doped polysilicon, a source electrode(100) for connecting a plurality of sources, and a common gate formed on a termination region. An ultra-low-dielectric(130) is formed between the gate oxide layer and the gate oxide layer which are formed in the doped polysilicon and the trench in order to reduce capacitance between the gate and the drain.
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