| 摘要 |
A delay-locked loop (DLL) circuit capable of decreasing power consumption is provided. A DLL circuit includes a delay line, an output buffer, a replica circuit, a phase detector, a shift register and a replica control circuit. The delay line delays an external clock signal for a determined time to generate a first signal. The output buffer buffers the first signal to generate an internal clock signal. The replica circuit delays the first signal for a determined time to generate a feedback signal. The phase detector compares the feedback signal with the external clock signal to generate a shift control signal. The shift register performs a shifting operation based on the shift control signal to generate the plurality of delay control bits. The replica control circuit generates a replica control signal based on the external clock signal and a lock signal, to control the replica circuit.
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