发明名称 Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
摘要 Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The ball-pads of one array, for example, are electrically coupled to the bond-pads of the corresponding die. The microelectronic workpiece of this embodiment further includes a protective film over the dielectric layer. In one embodiment, the workpiece further includes solder balls attached to corresponding ball-pads, and the protective film covers the dielectric layer in between the solder balls. The solder balls in this embodiment also have exposed contact sites such that the protective film can cover side portions of the solder balls but not a top surface of the solder balls.
申请公布号 US7218003(B2) 申请公布日期 2007.05.15
申请号 US20050090092 申请日期 2005.03.24
申请人 MICRON TECHNOLOGY, INC. 发明人 STORLI FARRAH J.
分类号 H01L23/52;H01L21/60;H01L23/31;H01L23/48;H01L23/485;H01L23/498;H01L23/525;H01L29/40 主分类号 H01L23/52
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