发明名称 |
PLL with controlled VCO bias |
摘要 |
In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock. Also provided is circuitry to maintain the VCO's bias level at a sufficient level if it is insufficient. Other embodiments may be disclosed herein.
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申请公布号 |
US2007046343(A1) |
申请公布日期 |
2007.03.01 |
申请号 |
US20050218207 |
申请日期 |
2005.08.31 |
申请人 |
KURD NASSER A;BARKATULLAH JAVED S |
发明人 |
KURD NASSER A.;BARKATULLAH JAVED S. |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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