发明名称 FLIP CHIP PACKAGE WITH REDUCED THERMAL STRESS
摘要 A flip-chip package includes a packaging substrate; an integrated circuit die affixed to the packaging substrate, wherein the integrated circuit die includes an active integrated circuit surrounded by a peripheral die seal ring therein; and a thermal stress releasing pad disposed in a stress-releasing area that is at a corner of the integrated circuit die outside the die seal ring, wherein the thermal stress releasing pad is connected to the packaging substrate by using a solder bump, which, in turn, is connected to a dummy heat-spreading metal plate embedded in the packaging substrate so as to form a heat shunting path for reducing thermal stress during temperature cycling test.
申请公布号 US2007023920(A1) 申请公布日期 2007.02.01
申请号 US20050161171 申请日期 2005.07.26
申请人 发明人 JAO JUI-MENG;KUO CHIEN-LI
分类号 H01L23/52 主分类号 H01L23/52
代理机构 代理人
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