According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The transaction assembler combines the request with one or more additional requests to access the two or more independently addressable subchannels within the channel and facilitates a speculative return of data from a subchannel for which a subchannel request is not available.
申请公布号
WO2007002445(A2)
申请公布日期
2007.01.04
申请号
WO2006US24546
申请日期
2006.06.23
申请人
INTEL CORPORATION;AKIYAMA, JAMES;CLIFFORD, WILLIAM