PHASE LOCKED LOOP AND METHOD

摘要

A phase locked loop circuit and a method of locking a phase are provided to generate clock signals of low frequency through a voltage control oscillator using a low control voltage, thereby reducing power consumption. A phase-difference detector(10) detects a phase difference between an input clock signal and a feedback output clock signal to generate an up signal and a down signal. A charge pump(12) pumps a charge in response to the up signal to increase a level of a control voltage, and pumps the charge in response to the down signal to lower the level of the control voltage. A voltage control oscillator(16') has at least two rings-shaped circuits connecting inversion circuits in a ring shape. The inversion circuit generates output clock signals having different phases.