| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which a width of an element isolation groove is miniaturized, and thereby, an MISFET can be miniaturized. <P>SOLUTION: A plurality of active regions which are enclosed with the element isolation groove 2 on a main surface of a substrate 1 and have a flat surface pattern in the shape of an island, are arranged at intervals in the first direction, respectively, and a semiconductor element is formed in each of a plurality of the active regions. The active regions, which are enclosed with the element isolation groove 2, have a convex rounded part in a peripheral portion. When the sum of a width a of the active region in the first direction and a interval b between the active regions constitutes a minimum pitch in the first direction, the width a of the active region in the first direction is larger than one-half of the minimum pitch, and the interval b is smaller than one-half of the minimum pitch. The minimum pitch is double minimum process dimension which is predetermined based on the resolution limit of photolithography technique. <P>COPYRIGHT: (C)2007,JPO&INPIT |
