发明名称 |
Method for the fast exploration of bus-based communication architectures at the cycle-count-accurate-at-transaction -boundaries (CCATB) abstraction |
摘要 |
A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model. The method calls are replaced by signals, and the functional blocks representing hardware components are further refined to obtain pin/cycle-accurate models which can be manually or automatically mapped to RTL, or be used to co-simulate with existing RTL components.
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申请公布号 |
US2006282233(A1) |
申请公布日期 |
2006.12.14 |
申请号 |
US20050139370 |
申请日期 |
2005.05.26 |
申请人 |
PASRICHA SUDEEP;DUTT NIKIL;BEN-ROMDHANE MOHAMED |
发明人 |
PASRICHA SUDEEP;DUTT NIKIL;BEN-ROMDHANE MOHAMED |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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地址 |
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