发明名称 TEST CIRCUIT FOR CLOCK GENERATING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To obtain a test circuit for a clock generating circuit that can perform sampling accurately equivalent to modulation cycles to shorten a measurement period and conduct an accurate function test of down-spread control as one modulating function of a spectrum spread clock generator (SSCG) by accurately testing a center frequency. <P>SOLUTION: A comparator 21 converts an analog modulated wave signal Sm from a modulated wave generating circuit 16 into a digital signal Sd and outputs it, a counter 22 counts cycles of a clock signal So outputted from the clock generating circuit according to the digital signal Sd, and a comparing circuit 25 compares the count value with a specification of the center frequency of the clock signal So set in a specification memory 24. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006333119(A) 申请公布日期 2006.12.07
申请号 JP20050154310 申请日期 2005.05.26
申请人 RICOH CO LTD 发明人 WATABE YUJI
分类号 H03K5/19;G01R31/28;G06F1/04;H01L21/822;H01L27/04;H03K4/06;H03L7/095;H03M1/34;H04L7/033 主分类号 H03K5/19
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