| 摘要 |
A PLL(Phase Locked Loop) frequency setting circuit is provided to reduce the size of the frequency setting circuit of a PLL by using regular property of channel number and frequency setting value. A frequency setting value of (k+m+n) bits set in a PLL(Phase Locked Loop) increases according to the increase of a channel number. When the channel number increases by x, the value of lower n bits of the frequency setting value returns to the original value and also the value of middle m bits increases by 1. A table(20) is composed of a memory having y and z which are quotient and a remainder of dividing the sum of an integer(a) and the channel number by x. An adding part(50) adds an initial value of the middle m bits of the frequency setting value and data y read from the table, and then outputs the result as a signal of the middle m bits of the frequency setting value. A selection part(40) selects a corresponding value of values of x kinds determined as the value of lower n bits of the frequency setting value, and outputs the selected value as a signal of lower n bits of the frequency setting value.
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