| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology for considerably reducing harmonic distortion by improving a switch characteristic in a SPDT switch. SOLUTION: Each of transistors Qtx1 to Qtx4, Qrx1 in the SPDT switch 2 comprises a dual gate FET provided with two gates, and resistors R6, R7, R15, R16, R23, R24 located among capacitors for gate withstanding power provided newly are respectively connected to the transistors Qtx1 to Qtx4, Qrx1 in addition to gate control voltage application resistors R2 to R5, R11 to R14, R20 to R22. The resistors R6, R7, R15, R16, R23, R24 change phases of voltages Vgs, Vgd applied to a gate-source capacitance Cgs and a gate-drain capacitance Cgd in the transistors Qtx1 to Qtx4, Qrx1 to reduce a harmonic distortion amount thereby. COPYRIGHT: (C)2007,JPO&INPIT
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