HIGH DENSITY SEMICONDUCTOR MEMORY CELL AND MEMORY ARRAY USING A SINGLE TRANSISTOR

摘要

A programmable memory cell (102-Figure 1) comprised of a transistor (104) located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate (310-Figure 3) formed from the column bitline and its source (306) connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region (501-Figure 5) in the substrate underlying the gate of the transistor.