发明名称 TILED PREFETCHED AND CACHED DEPTH BUFFER
摘要 <p>A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.</p>
申请公布号 WO2006102380(A1) 申请公布日期 2006.09.28
申请号 WO2006US10340 申请日期 2006.03.21
申请人 QUALCOMM INCORPORATED;ANDERSON, MICHAEL HUGH;CHUANG, DAN MINGLUN;SHIPPEE, GEOFFREY;DHAWAN, RAJAT RAJINDERKUMAR 发明人 ANDERSON, MICHAEL HUGH;CHUANG, DAN MINGLUN;SHIPPEE, GEOFFREY;DHAWAN, RAJAT RAJINDERKUMAR
分类号 G06T15/00 主分类号 G06T15/00
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