发明名称
摘要 <p>The invention provides a method of controlling a jitter buffer, which sets a packet delete area, a packet add area, and a clock control area inside a FIFO forming the jitter buffer. The method controls to delete packets when the stored packet quantity is within the packet delete area, controls to add packets when the stored packet quantity is within the packet add area, and controls to raise or lower the clock frequency for reading the packets when the stored packet quantity is within the clock control area, in which the clock control area is set between the packet add area and the packet delete area.</p>
申请公布号 JP3825007(B2) 申请公布日期 2006.09.20
申请号 JP20030064995 申请日期 2003.03.11
申请人 发明人
分类号 H04L12/885;H04L12/64;H04L12/835;H04L29/06 主分类号 H04L12/885
代理机构 代理人
主权项
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