发明名称 |
Method and circuit configuration for synchronous resetting of a multiple clock domain circuit |
摘要 |
A method and circuit configuration for synchronous resetting of an multiple clock domain circuit such as an Application Specific Integrated Circuit (ASIC) combine an asynchronous reset signal with a functional signal using a clocked reset tree of synchronous logic elements.
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申请公布号 |
US2006145738(A1) |
申请公布日期 |
2006.07.06 |
申请号 |
US20040027906 |
申请日期 |
2004.12.30 |
申请人 |
HEINKEL ULRICH;RUPPRECHT WOLFGANG;SMALLA CHRISTOPH |
发明人 |
HEINKEL ULRICH;RUPPRECHT WOLFGANG;SMALLA CHRISTOPH |
分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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