| 摘要 |
<P>PROBLEM TO BE SOLVED: To prevent variation in phase of a clock signal, the variation being caused by a process factor. <P>SOLUTION: In a signal-generating circuit 100, one or more clock buffers 31 are arranged on a clock signal line 30 through which a clock signal PLLCK passes, and the clock signal PLLCK is delayed by the one or more clock buffers 31, and then a prescribed signal is generated on the basis of the delayed clock signal. The signal-generating circuit 100 includes: a clock buffer 40 for reference which has a plurality of clock buffers 41 formed on the same chip as the clock buffer 31; a delay-detecting circuit 50 which detects the delay quantity of the clock buffer 40 for reference and outputs a phase adjusting signal PHADJ based on a difference between the delay quantity and a predetermined delay quantity; and a phase-adjusting circuit 20 which changes the phase of the clock signal PLLCK in accordance with the phase adjusting signal PHADJ. <P>COPYRIGHT: (C)2010,JPO&INPIT |
