| 摘要 |
PROBLEM TO BE SOLVED: To prevent a decimation filter from being increased in its circuit scale even when a degree or the number of stages of aΔΣmodulator or the number of stages of a combline filter is increased. SOLUTION: An output of aΔΣtype A/D converter 201 is formed into address bit sequence by an address decoder, so that multiplication in a digital filter 206 is performed by a conversion table 212. Thus, even if the degree or the number of stages of aΔΣdemodulator or the number of stages of a combline filter is increased, the number of shift registers 211 used for a decimation filter 202 is reduced, thereby suppressing the expansion of circuit scale. COPYRIGHT: (C)2006,JPO&NCIPI
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