Synchronization of clock signals in a multi-clock domain

摘要

A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge in an input clock signal after a logic low corresponding to a prior negative edge is propagated to as a synchronized signal, and provides a logic high as an input to a sampling module. The sampling module propagates the signal led at the input as the synchronized signal. The adaptive module causing the input to remain at logic high at least until the synchronization module provides logic level as the synchronized signal. The negative edges in the input signal may also be processed similarly.