Semiconductor memeory device having data input/output circuit capable of reducing data writing number during memory test and the test method of the same,申请号KR19990019983-传众专利搜索

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发明名称	Semiconductor memeory device having data input/output circuit capable of reducing data writing number during memory test and the test method of the same
摘要
申请公布号	KR100574918(B1)	申请公布日期	2006.05.02
申请号	KR19990019983	申请日期	1999.06.01
申请人		发明人
分类号	G11C29/00	主分类号	G11C29/00
代理机构		代理人
主权项
地址

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