APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE OF INTEGRATED CIRCUITS
摘要
A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
申请公布号
WO2005116878(A3)
申请公布日期
2006.04.27
申请号
WO2005US17265
申请日期
2005.05.18
申请人
ALTERA CORPORATION;LEWIS, DAVID;BETZ, VAUGHN;RAHIM, IRFAN;MCELHENY, PETER;LIU, YOW-JUANG, W.;PEDERSEN, BRUCE
发明人
LEWIS, DAVID;BETZ, VAUGHN;RAHIM, IRFAN;MCELHENY, PETER;LIU, YOW-JUANG, W.;PEDERSEN, BRUCE