PROGRAMMABLE LOGIC AUTO WRITE-BACK

摘要

A first configuration controller (115) loads configuration data into a programmable logic device 105). The first controller is coupled with a first configuration memory (via path 145) and manages couplings of the memory to a first load path (110). The load path (110) couples to a latch ring (130), which receives configuration data from the first memory. An array of configuration latches (125) receives the configuration from the latch ring (130) and effects a configuration of the programmable device (105). A write-back path (155) couples the latch ring (130) and first configuration memory. A write-back controller (150) manages write-back operations of configuration data from the latch ring (130) to the configuration memory. In another embodiment, the write-back controller (350) is coupled to a second (internal) configuration memory (320), which is coupled to a second load path (310) that is coupled to the latch ring.