| 摘要 |
To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference DeltaV between data "0" and data "1" can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.
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