发明名称 System and scanout circuits with error resilience circuit
摘要 In one embodiment, an apparatus is provided with a system circuit, a scanout circuit and an error detecting circuit. The system circuit is adapted to generate a first output signal in response to a data input signal and a system clock signal. The scanout circuit is adapted to generate a second output signal in response the data input signal and the system clock signal. The error detecting circuit, coupled to the system circuit and the scanout circuit, is adapted to generate an error signal in response to a relative condition between the first output signal and the second output signal.
申请公布号 US2006005103(A1) 申请公布日期 2006.01.05
申请号 US20050050996 申请日期 2005.02.04
申请人 INTEL CORPORATION 发明人 ZHANG MING;MITRA SUBHASISH;MAK TAK M.;ZIA VICTOR
分类号 G01R31/28;H03M13/00 主分类号 G01R31/28
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