| 摘要 |
PROBLEM TO BE SOLVED: To provide a device structure and its fabrication method capable of realizing a high withstand voltage MOS transistor where p- and n-channels have a high withstand voltage in the same chip. SOLUTION: This is a semiconductor device having a high withstand voltage MOS device structure composed of an n-channel L-DMOS 101, a p-channel L-DMOS 102, and a logic part 103. The n-channel L-DMOS 101 comprises respective components of an n-type drift region 12, a p well 19, a p-type high concentration diffusion layer 20, a source diffusion layer 21, a drain diffusion layer 22, a source contact 14, a drain contact 16, a source wiring 15, a drain electrode 17, and a gate electrode 18. The source electrode 14 of the n-channel L-DMOS 101 formed in the n-type drift region 12 being an SOI region and the region 11 are brought into an electric continuity so as to have the same potential. COPYRIGHT: (C)2006,JPO&NCIPI
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