| 摘要 |
On a clock supply route to a specified block such as a ROM, there are provided a clock delay circuit which includes a plurality of delay elements connected in series and a selector, such that a delay clock signal is selected and output in accordance with a delay control signal. During a product test, an operation test for the specified block is carried out in order to find out the delay adjustment signal that exhibits a proper operation. For this purpose, the delay adjustment signal is supplied from a delay adjustment terminal via a selector. When a value of the delay adjustment signal is obtained in the product test, the value of the delay adjustment signal is memorized to a delay setting circuit including a fuse circuit or a PROM. In a normal operation, the memorized value in the delay setting circuit is supplied to the clock delay circuit via the selector.
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