| 摘要 |
Efficient design to implement min**/min**- or max**/max**- functions in LDPC (Low Density Parity Check) decoders. When compared to prior art approaches, the novel and efficient implementation presented herein allows for the use of substantially less hardware and surface area within an actual communication device implemented to perform these calculations. In certain embodiments, the min** processing (and/or max** processing) is implemented to assist in the computationally intensive calculations required to decoded LDPC coded signals. In one instance, this is operable to assist in check node processing when decoding LDPC coded signals. However, the efficient principles and architectures presented herein may be implemented within other communication device types to decode other types of coded signals as well. For example, the processing presented herein may perform calculations within a variety of decoders including LDPC decoders, turbo decoders, TTCM decoders, and/or other decoder types without departing from the scope and spirit of the invention.
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