A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass filter. The second latch further includes a differential pair of transistors. Each of the transistors include a drain, a source and a gate. The gates of the at least two transistors configured to receive a signal generated by the first latch. Additionally, the gates of the at least two other transistors are coupled to a control signal for determining a low-pass characteristic of the second latch.
申请公布号
WO2005091506(A1)
申请公布日期
2005.09.29
申请号
WO2005IB50818
申请日期
2005.03.04
申请人
KONINKLIJKE PHILIPS ELECTRONICS N.V.;LEENAERTS, DOMINICUS, M., W.;NAUTA, BRAM;ACAR, MUSTAFA
发明人
LEENAERTS, DOMINICUS, M., W.;NAUTA, BRAM;ACAR, MUSTAFA