发明名称 JITTER ATTENUATOR AND PHASE SYNCHRONIZATION OSCILLATION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a jitter attenuator capable of generating a reference clock wherein the effect of input jitter is suppressed without the need for mount of an arithmetic processing circuit for performing statistic processing such as moving average. <P>SOLUTION: The jitter attenuator is provided with an up-counter 3 for counting number of pulses of an input clock f<SB>in</SB>and resetting the count of the number of pulses when receiving a frequency division signal of a high speed clock f<SB>h</SB>, and receives the count just before the reset from the up-counter 3 and frequency-divides the high speed clock f<SB>h</SB>by the count to generate the reference clock f<SB>ref</SB>. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005184250(A) 申请公布日期 2005.07.07
申请号 JP20030419866 申请日期 2003.12.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 DOMOTO YUKINORI
分类号 H03L7/08 主分类号 H03L7/08
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