发明名称 BITE-LINE DROOP REDUCTION
摘要 Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.
申请公布号 US2005146956(A1) 申请公布日期 2005.07.07
申请号 US20030746148 申请日期 2003.12.24
申请人 SOMASEKHAR DINESH;YE YIBIN;KHELLAH MUHAMMAD M.;PAILLET FABRICE;TANG STEPHEN H.;KESHAVARZI ALI;LU SHIH-LIEN L.;DE VIVEK K. 发明人 SOMASEKHAR DINESH;YE YIBIN;KHELLAH MUHAMMAD M.;PAILLET FABRICE;TANG STEPHEN H.;KESHAVARZI ALI;LU SHIH-LIEN L.;DE VIVEK K.
分类号 G11C7/00;G11C7/12;(IPC1-7):G11C7/00 主分类号 G11C7/00
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