| 摘要 |
PURPOSE: A semiconductor integrated circuit device is provided to planarize a wiring layer and restrict a parasitic capacitance between wires by forming a dummy pattern with the same material as the wiring layer. CONSTITUTION: A multi-layered wiring structure including a plurality of wiring layers(3,5) is formed on a semiconductor substrate. A dummy pattern(3D) is formed between the wiring layers in order to planarize the wiring layers. The dummy patterns are formed with the same materials as the wiring layers. The dummy pattern is shaped to reduce a capacitance produced between the dummy pattern and the adjacent wiring layer. The dummy pattern is formed with a shaped of polygonal prism having a side, which is opposite to the adjacent wiring layer and is not parallel to the adjacent wiring layer. |
