发明名称 |
Method for fabricating a high-voltage high-power integrated circuit device |
摘要 |
The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.
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申请公布号 |
US6855581(B2) |
申请公布日期 |
2005.02.15 |
申请号 |
US20020153975 |
申请日期 |
2002.05.23 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
ROH TAE MOON;LEE DAE WOO;YANG YIL SUK;PARK IL YONG;KIM SANG GI;KOO JIN GUN;KIM JONG DAE |
分类号 |
H01L21/84;H01L27/12;(IPC1-7):H01L21/84 |
主分类号 |
H01L21/84 |
代理机构 |
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