ARRAY OF NANOSCOPIC MOSFET TRANSISTORS AND FABRICATION METHODS

摘要

A nanoscopic transistor (20) is made by forming an oxide layer on a semiconductor substrate (S10, S20), applying resist (S30), patterning the resist using imprint lithography to form a pattern aligned along a first direction (S40), applying a first ion-masking material over the pattern (S50), selectively lifting it off to leave a first ion mask to form a gate (S60), forming doped regions by implanting a suitable dopant (S70), applying another layer of resist (S90) and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction (S100), applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern (S120), and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask (S130). The method may be used to make an array (10 or 15) of nanoscopic transistors (20).