| 摘要 |
PROBLEM TO BE SOLVED: To efficiently transmit data inside a memory accessed by a plurality of processors to another memory. SOLUTION: An upstream side processor unit 1 is provided with the memory 8, the processor 9, a memory access controller 11 and a transmission part 20. A downstream side processor unit 2 is provided with the memory 111, the processor 116 and a reception part 101. The memory of the upstream side processor unit can be accessed from a host processor unit 4, the processor 9 and the memory access controller 11 and the memory of the downstream side processor unit can be accessed from the host processor unit, the processor 116 and the reception part. The reception part is provided with a FIFO memory 103. The memory access controller writes the data inside the memory 8 through the transmission part to the FIFO memory inside the reception part. The reception part writes the data inside the FIFO memory to the memory 111. COPYRIGHT: (C)2005,JPO&NCIPI
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