| 摘要 |
An integrated circuit parallel multiplication circuit delivers both natural multiplication products and polynomial products with coefficients over GF(2). The parallel multiplier hardware architecture (Fig. 3) arranges the addition of partial products (Pi, j) so that it begins in a first group of adder stages (23) that perform additions without receiving any carry terms as inputs, and so that addition of the carry terms (ek+1) is deferred until a second group of adder stages (29) is arranged to follow the first group. This intentional arrangement of the adders into two separate groups allows both the polynomial product (dk) to be extracted from the results (sk) of the first group of additions, and the natural product (ck) to be extracted from the results of the second group of additions. |
