| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the power consumption by reducing surplus wiring in a main bit line in a semiconductor integrated circuit including the memory array of a bit division type RAM. <P>SOLUTION: The semiconductor integrated circuit is provided with a first group of memory cells MC00-MC0N and a second group of memory cells MC10-MC1N arranged in one row; a first group of word lines WL00-WL0N and a second group of word lines WL10-WL1N; a first set of sub bit lines SBL0, SBL0 bar, and a second set of sub bit lines SBL1, SBL1 bar; a set of main bit lines MBL, MBL bar that are not extended at both the sides in the column direction of the first group of memory cells; and bit division circuits 10, 20 for selectively connecting one of the first set of sub bit lines and the second set of sub bit lines to one set of main bit lines. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
